Affichage des articles dont le libellé est IB-S56USB. Afficher tous les articles
Affichage des articles dont le libellé est IB-S56USB. Afficher tous les articles

jeudi 9 juillet 2026

Some headway despite the heatwave.

Despite this intense heat, I managed to make some progress on my developments. And to kick things off, a magnificent failure. Well, it's still progress, I suppose. This concerns the USB expansion board for the Akai S5000/S6000 sampler. My first prototype doesn't work at all. Mind you, that does make it easier to find the cause. I did indeed make a beginner's mistake on the PCB. It's so obvious, even though I checked my schematic several times, that I'm simply not going to reveal it. So I've corrected my circuit. Now I just need to get it re-fabricated.

There's no visible difference on this new board, except that I've moved the USB-C connector out a bit more, because once the current board is installed in the sampler, I realized it was missing just a tiny millimeter to properly plug in an external cable.

Luckily, I do have some genuine progress to report, particularly with the MSX cartridge. I won't recount the whole development story of this project here, but suffice it to say that I recently moved over to FPGA. For that purpose, I switched to an Efinix TRION FPGA. These FPGAs are new to me and are a little trickier to implement than the GoWin FPGAs I used before, but they're also less expensive.

Given the tight space constraints of an MSX cartridge, and since I'm using a 144-pin device, I had to opt for a four-layer PCB. The first spin of this board isn't perfect, but it's still well enough laid out to allow programming the FPGA through its JTAG port.


The image below shows the result of programming the FPGA via JTAG. In reality, it's a little more involved than that. Using the JTAG interface alone, you can program the FPGA's internal RAM 'on the fly'—which is great for development. However, it also means that whenever the FPGA is reset or powered off for any reason, that RAM is wiped, and the FPGA then expects to find an external EEPROM holding the configuration bitstream to reload its internal RAM and boot up. This is called SPI ACTIVE mode, because the FPGA itself initiates and manages the copying process from the external EEPROM.

So how do you program that EEPROM when you haven't added a dedicated connector for an external SPI programmer? The answer is simply to use 'SPI over JTAG' mode. And that's where the magic happens. During programming, the bitstream is written directly into the SPI EEPROM through the JTAG port. Once that's done, a simple reset of the FPGA is all it takes for it to fetch its configuration from the EEPROM—and that's exactly what this image illustrates.

Here's what my development setup looks like:


I should also mention that to program this FPGA, I'm using a commercial interface I bought myself on Aliexpress JTAG probe. Although it comes with the FTDI chip, it doesn't quite meet the specific requirements for programming the Efinix FPGA. One signal is missing from the output connector, but luckily that signal is available on the internal connector on the PCB. You just have to route that signal to the external connector, and the interface works flawlessly in JTAG mode with the Efinix programming software.

View of the programmer interface:


I'm quite pleased to have gotten this far from the initial study I did on an Efinix test board. It feels like years have passed since my successful tests back in December 2025, even though it's only been just over six months. Since then, I've made a lot of progress with VHDL and have other developments underway. Needless to say, I'm once again having to go back to the drawing board when it comes to implementing the Drumulator in FPGA. Plus, with the constraint I've imposed on myself to use as few American components as possible—would that force me to find other solutions? No, it encourages me to do so. And this constraint actually opens up potentially more interesting avenues. I have a few tests to run regarding the digital-to-analog conversion of the Drumulator, and I hope to be able to decide on the new direction to take based on the results of those tests.

My MSX development system in December 2025:


Despite a few hiccups that come with electronics development—especially since I'm more of a weekend hobbyist than a fully certified engineer—I'm pretty happy with the result. But still, I feel it's not going as fast as I'd like. I hope to ramp up my efficiency over the coming months.