I've been testing the Wichit Sirichote's µPF--1 compatible development board for a few years now.
Here are all the studies carried out around this system:
- 2017 - Achievement of the kit with the basic system available in 2017.
- 2018 - Attempted modification with the system update: large number of malfunctions including the serial link.
- 2019 - Study of the system on a commercial FPGA board. Modification of the code for a functional serial link.
- 2020 - Realization of a personal board based on Intel FPGA and installation of the system with the operation of the serial link corrected.
- 2022 - Porting VHDL code to GoWin FPGA. The goal is to test the operation of these new FPGAs.
Until now, I had only taken care of the rewriting of the code of Wichit Sirichote concerning the operation of the serial link. I had not particularly tested the other functions of the monitor other than those relating to the ADDR and DATA keys, allowing the contents of a memory address to be viewed, and to be modified if necessary.
On the occasion of the transition to the GoWin FPGA, I decided to test all the keys allowing autonomous operation of the system. And there, big surprise. The code is buggy everywhere!!!
Until now I thought the problems were mostly around the serial port. actually no. I almost have to re-write the whole system.
In fact: Wichit Sirichote provides the Hexa file of the first version of the system. The source is only provided for the latest version, the one where the serial port does not work.
After having worked hard on this source code, I think that this source is in fact a very first development version and does not correspond to the first version provided, nor to the very last one.
If the source provided allows you to get a good idea of how the system works, it is so badly written and so dysfunctional that everything has to be rewritten.
Even getting to this error message (generated on purpose for the photo), it wasn't easy. I chose an end address lower than the start address for the memory block copy function. What generates this error!
In a nutshell: Wichit Sirichote's idea was very good. But do not try to draw inspiration from the sources provided to make your own monitor. It's a guaranteed waste of time. It is better to develop your own monitor from scratch!
Apart from the REL key, the function of which I am unable to determine what it does, even from the source, all the functions except the DUMP and the LOAD are functional. In particular the step-by-step function which involves the use of the NMI interrupt of the processor.
It only remains for me to implement the serial link for the LOAD/DUMP function in the FPGA and to copy all the modifications that I have already made to the source concerning the management of this serial port.
I wanted to see if I could make the same type of system with the GoWin FPGAs as with those from Intel that I usually use. I must say the result is absolutely perfect.
I had to write a small utility to provide the RAM initialization file in GoWin format. Nothing too complicated to do. Thereafter, the development procedure is carried out in the same way as with the Quartus development chain.
I will quietly finalize the development of this system and will test everything concerning the HDMI outputs because GoWin seemed to provide this type of output on its FPGAs. In fact, now that I'm in a position to develop a relatively complex but basic system, I would really try to build a more standard small computer, i.e. with a normal keyboard and video output...
I had to develop a Drumulator clone, but given the power of these FPGAs, I'm going directly to develop an SP12 or SP1200 clone. As I tested all the sub-elements of the Drumulator, it shouldn't be too complicated to get started with the SP12/SP1200 since it's exactly the same operating principle, but in 12 bits...
