Some headway despite the heatwave.

Despite this intense heat, I managed to make some progress on my developments. And to kick things off, a magnificent failure. Well, it's still progress, I suppose. This concerns the USB expansion board for the Akai S5000/S6000 sampler. My first prototype doesn't work at all. Mind you, that does make it easier to find the cause. I did indeed make a beginner's mistake on the PCB. It's so obvious, even though I checked my schematic several times, that I'm simply not going to reveal it. So I've corrected my circuit. Now I just need to get it re-fabricated.

There's no visible difference on this new board, except that I've moved the USB-C connector out a bit more, because once the current board is installed in the sampler, I realized it was missing just a tiny millimeter to properly plug in an external cable.

Luckily, I do have some genuine progress to report, particularly with the MSX cartridge. I won't recount the whole development story of this project here, but suffice it to say that I recently moved over to FPGA. For that purpose, I switched to an Efinix TRION FPGA. These FPGAs are new to me and are a little trickier to implement than the GoWin FPGAs I used before, but they're also less expensive.

Given the tight space constraints of an MSX cartridge, and since I'm using a 144-pin device, I had to opt for a four-layer PCB. The first spin of this board isn't perfect, but it's still well enough laid out to allow programming the FPGA through its JTAG port.

The image below shows the result of programming the FPGA via JTAG. In reality, it's a little more involved than that. Using the JTAG interface alone, you can program the FPGA's internal RAM 'on the fly'—which is great for development. However, it also means that whenever the FPGA is reset or powered off for any reason, that RAM is wiped, and the FPGA then expects to find an external EEPROM holding the configuration bitstream to reload its internal RAM and boot up. This is called SPI ACTIVE mode, because the FPGA itself initiates and manages the copying process from the external EEPROM.

So how do you program that EEPROM when you haven't added a dedicated connector for an external SPI programmer? The answer is simply to use 'SPI over JTAG' mode. And that's where the magic happens. During programming, the bitstream is written directly into the SPI EEPROM through the JTAG port. Once that's done, a simple reset of the FPGA is all it takes for it to fetch its configuration from the EEPROM—and that's exactly what this image illustrates.

Here's what my development setup looks like:

I should also mention that to program this FPGA, I'm using a commercial interface I bought myself on Aliexpress JTAG probe. Although it comes with the FTDI chip, it doesn't quite meet the specific requirements for programming the Efinix FPGA. One signal is missing from the output connector, but luckily that signal is available on the internal connector on the PCB. You just have to route that signal to the external connector, and the interface works flawlessly in JTAG mode with the Efinix programming software.

View of the programmer interface:

I'm quite pleased to have gotten this far from the initial study I did on an Efinix test board. It feels like years have passed since my successful tests back in December 2025, even though it's only been just over six months. Since then, I've made a lot of progress with VHDL and have other developments underway. Needless to say, I'm once again having to go back to the drawing board when it comes to implementing the Drumulator in FPGA. Plus, with the constraint I've imposed on myself to use as few American components as possible—would that force me to find other solutions? No, it encourages me to do so. And this constraint actually opens up potentially more interesting avenues. I have a few tests to run regarding the digital-to-analog conversion of the Drumulator, and I hope to be able to decide on the new direction to take based on the results of those tests.

My MSX development system in December 2025:

Despite a few hiccups that come with electronics development—especially since I'm more of a weekend hobbyist than a fully certified engineer—I'm pretty happy with the result. But still, I feel it's not going as fast as I'd like. I hope to ramp up my efficiency over the coming months.

Today's thought: US tariffs applied to France. Thank you, Donald Trump.

Today's reflection: US customs duties.

I really enjoy retro-computing. The question I hadn't really settled until now was: with retro components or with modern components? After the Z80 disappeared, the only 8-bit family left was the 6502, still manufactured by Western Design Center (WDC).

I'm currently spending some of my free time on the little Cody computer and the Memo-1, both based on the W65C02S from WDC. On the other hand, I also took an interest in the Commander X16, also based on the W65C02S, because I found that machine interesting.

To keep going with the subject and especially to build the Memo-1 board, I just placed an order for a few W65C02S processors and peripheral circuits from Mouser.

And this morning, the big surprise. Between the shipping costs and the taxes already paid, which already came to €28 for a total component price of €67.35—i.e., fees equivalent to 41.5% of the product amount—UPS has just billed me €49.14 in customs duties. The total fees for this order therefore amount to €77.14, or 114.53% of the value of the goods.

To be perfectly clear about that last sentence: I paid €77.14 in shipping, taxes, and customs fees for a component total of €67.35.

This is quite simply armed robbery. That reminds me exactly of Apple's business practices, which is why I have never bought any Apple products.

- My decision is simple: components of this kind from the United States—It's over.
- Retro-computing with retro components—It's over.
Period.

Americans are definitely no longer my friends!

Thanks to whom?
Thanks, Donald! 

Memo-1

In the series "other distracting activities during the heatwave," I looked into the very simple development by a "local guy"—that is, a Frenchman—who created a small computer based on the 6502 processor, with the particularity of being able to connect to the French Minitel. I always appreciate seeing this precursor of networked computing, the Minitel, being put to use. The capabilities of this machine were very limited. The major consequence was that for more than fifteen years, very simple and highly standardized "digital" applications were developed, which enabled French businesses to rapidly increase their efficiency. Imagine: a very simple interface whose learning curve—just a few dozen minutes—was enough to acquire the reflexes needed for a significant boost in usage efficiency. No stress for the user, the "graphical" interface never introduced any uncertainty. And what about security? Point-to-point connections with no possibility of hacking, unless one broke into Transpac distribution points, which were moreover equipped with non-standard hardware to even attempt sniffing a communication. How things have changed. Using Microsoft's online typewriter, um... yes... why not! And will this still be useful with AI?

I suggest you take a quick look at his YouTube page: Memo-1

I grabbed a few screenshots from his YouTube page.

Charming little board, isn't it?

As usual, its format is proprietary. The author took as an example the format of the old cardboard programming cards that were found on virtually all programmable computers of the era, notably the 80-column IBM cards. The problem with all these cards in incompatible formats is that once the board is assembled and tested, well, you put it away and move on... to the next one. As a result, you accumulate these boards and end up forgetting about them. And when you take them out of the drawers again, you still have to find or rediscover the specific connectors, the power supply, the USB-to-serial converter, etc.

So, for the past few months now, I have decided to take the boards I found interesting and remake them in the Euro RACK format. That way, it will "just" be a matter of getting a RACK with a backplane board and a standard power supply, and the boards can be inserted into the available slots, remaining easily accessible at all times, and, of course, stored in the same place. I have always found the TI99/4A's bus expansion system particularly interesting.

Gorgeous!

So I took the MEMO‑1 schematic and redrew it, replacing the expansion connector with a backplane bus connector. I also added a real‑time clock connected to the VIA via the I²C bus, which will need to be implemented using the VIA's I/O ports. This will require some specific programming that can be done later. As for the backplane bus pinout, I adopted the EuroBEEB format, since that system also used a 6502. This results in a board that is fairly easy to build and has a compact form factor.
 

On the original MEMO‑1 system, the expansion connector is designed to accept a cartridge. This will obviously not be possible with the backplane bus. It will therefore be necessary to design another small board that brings the essential signals to the front face of the rack, fitted with a cartridge connector. 

Regarding the Cody computer, which I also mention in this blog, I intend to convert it to a rack format as well. Since Cody has even fewer components, this shouldn't be very difficult, even if I incorporate the USB keyboard adapter.

These two systems, as well as the EuroBEEB board, are all based on the 6502, or its more modern version, still available from the Western Design Center. For now, I have nothing planned based on the Z80 processor, since it is no longer in production. However, since I have used Z80 cores in FPGAs in the past, I might be able to perform the same kind of conversion for Sergey Kiselev's CP/M-compatible board : Easy_z80 .

CODY computer

Between two "high-tech" developments, back to pure 80s style. This is about adapting a USB keyboard to the computer developed by Frederick John Milens, which I have already mentioned on this blog.

And no, for now I haven't done anything at all with this machine. I just built one copy because I think the whole package created by Frederick is absolutely brilliant. And I mean it. For anyone who wants to acquire the basics of digital electronics and fundamental computing, the machine, along with its documentation, is absolutely brilliant.

Moreover, the creator of Cody uses a whole ecosystem that is easy to get to grips with and completely free. Since all the sources are provided on GitHub, it is relatively easy to modify all or part of the design. And that is what I am going to present here.

As for me, I did not build the machine's keyboard. It is an extra cost and I prefer to use a basic USB keyboard. This is a purely personal choice. I am not interested in taking the retro concept all the way to the end. For me, the spirit matters above all.

So, to adapt a USB keyboard to this machine, the tactic I use is that of the cuckoo. Yes, the one that steals other birds' nests to build its own.

The idea is therefore to slightly modify the computer's hardware as well as the software that runs the machine. 

The concept of my build is very simple.
I use a USB keyboard to serial port converter module.
I use a small processor to convert this serial code into parallel code, which I then present on the Cody's data bus using a bus driver circuit. 

I am modifying Frederick's BASIC, written in 6502 assembly, to take into account not the scanning of its matrix keyboard, but rather the data coming from my small adapter board. Since the source is well documented, it is easy to make this type of modification. Although I have never used 6502 assembly before, I must say it is incredibly simple, even compared to the Z80. I am using TASM to assemble the source.

My system.

There are no modifications to be made in the Cody SPIN source, because the VIA that normally handles the keyboard matrix has a 256-byte address range, whereas only 16 are actually used. So I took bit A4 of the address bus to differentiate between an access to the VIA or to my board. This is the only physical modification I made.

In the ASM 6502 source, I added a constant representing the base address of my board. From then on, the function that retrieves a valid key code from the matrix keyboard boils down to:

KEYDECODE LDA KBD_CTRL     ; Reads the controller output into A
                         STA KEYCODE        ; Stores A into KEYCODE
                         RTS

Moreover, the KEYTOCHR function no longer does anything and returns immediately since there is no code conversion to perform, as I am doing this conversion directly on my small processor board.

Note that since I don't really know how the two special modifier keys are used, I may have to modify my system accordingly. 

But for now, this is enough for me to validate that my setup works.

The final procedure therefore consists, from a software standpoint, of assembling the BASIC source using TASM, recompiling the Cody SPIN project using Parallax's Propeller Tool, and loading the result into the Cody board. What's great about the Propeller chip is that all tests can be run in RAM, before saving the final code to EEPROM. Parallax's tool is remarkably easy to use.

I am using a RISC-V processor and its associated development IDE, MounRiver Studio. I have completed a number of projects with these tools and I must say that the latest version of the IDE is even more efficient, practical, and pleasant to use. In short, I don't regret the time I spent a few years ago discovering these processors.

Anyway, once everything is set up, it is fairly easy to achieve the expected result. I only spent a few hours of pure hobby time developing this adapter.

Validation of my concept.

And there you have it, the basics are working. All that remains for me to do is to complete the software part to fully emulate the original keyboard.

I really don't know where I'm going with this!

Implementing an FPGA isn't very complicated in itself. Whether on the hardware or software side, all it 'takes' is the right learning and a little (or a lot of) motivation to get there. No, it's rather what comes after that gets tricky. The potential of these types of circuits is so vast that you can consider using them in a huge number of applications. The problem then boils down to development cost. It's tempting to pack as much logic as possible into the FPGA. As a result, you quickly find yourself needing a chip with a good number of I/Os, and therefore a large pin count — and thus, a BGA package.

The development cost of a PCB designed to host a BGA-packaged FPGA is not the same as that of a board equipped with a small microcontroller. Nor are the risks of malfunction.

Considering that my field is more on the 'mixed' side — that is, both digital logic and analog — I find it risky to dive into the design of large PCBs containing a BGA package. I prefer to go the module route. That is, to focus specific efforts on the most precise sub-assemblies possible.

I'll take my process of putting the Drumulator into an FPGA as an example. Designing a relatively large PCB with a BGA seems inappropriate for an amateur-style build. So I decided to create an FPGA module tailored to my needs. I should mention that I've already built this kind of module with GoWin FPGAs, but in a 144-pin package. As a result, I didn't implement any memory on that module at all. However, with the goal of providing a complete computing core, I need memory.

So I went with an implementation using a TRION FPGA coupled with static RAM, an EEPROM for storage, a real-time clock, and a battery for backing up the memory and time.

Obviously, I couldn't get away with a two-layer PCB this time. This time, it's four layers. To keep manufacturing costs acceptable, I'm also forced to use through-hole vias, which complicates the board design.

But anyway, after a certain amount of time, I managed to produce the design for the board I want to build.

 

I have to admit that it took me a while to route the entire board. I think I've done a better job than I did with the MSX cartridge. I suppose that's normal — it takes experience, and experience only comes through iteration.

That said, on this board, I paid particular attention to the connections between the FPGA and the SRAM. The traces are short, and I matched the lengths of all bus signals, so that a fairly high operating frequency can be used.

As for the available I/O connectors, generally speaking, the traces on the 'component' side will be fairly fast since they won't encounter any vias. That should compensate for the signal integrity loss caused by longer trace lengths. The other signals will have at least one via along the path, and some of them two, though the latter case is very rare.

I have no idea how I'm going to actually assemble this board. The PCB manufacturer I work with doesn't stock Efinix FPGAs. So either I find another supplier capable of assembling these FPGAs, or I mount them myself. In which case, I'll need to get a hot plate to solder the main components.

Moreover, I don't know whether the wiring as it stands will actually allow the JTAG programmer to work properly. To figure that out, I need to wait until I implement the MSX cartridge, so I can verify that the power supply I've set up is correctly matched to the FPGA, and that the JTAG connections are properly made.

So, designing this board has already been an adventure. I was really skeptical about whether I'd even get to the end of it. Assembling this board is going to be a new adventure. But hey, if I really want to move beyond the 'Sunday tinkerer' phase, I have to take it to the next level. And since I've now gained a good command of VHDL coding, I no longer have a choice — I have to go for it.

 

And now for something completely different!

While waiting to receive the printed circuit board for the MSX cartridge, I started working on making a compatible USB card for the AKAI S5000/S6000 samplers.

The reason is that I know someone who is developing a new version of AKSYS that works perfectly under Windows 10 & 11. It turns out that not all Akai S5/6000 machines were shipped with this card. That's a shame.

So I studied the card I own and looked into whether it might be possible to create a new version.

It turns out that it is.

On the one hand, a USB component compatible with the one on the original USB card still exists today. And on the other hand, I was able to retrieve the logic equations of the PAL chip that is on this card.

For now, these equations seem to be correct, since I was able to repair another original but faulty USB card using a GAL programmed with my equations. So I am hopeful that this will work, even though the decoding performed by the original PAL is quite unusual.

The card's schematic is also unusual. Without going into too much detail, some functions are implemented by first latching a kind of register — registers made out of resistors and capacitors.

In short, the read and write functions are not direct but require going through other operations first.

In any case, I have completed the schematic and then the PCB for this card :

So, I have no idea whether this new card will work or not. The only way is to test it and compare the signals with the original card if it doesn't work.

Next steps after the first tests....

New batch of triple output PSU, for not only the PROPHET-VS!

A few years ago, I developed a regulated power supply with three outputs: +5V, +12V, and -12V, primarily intended to replace the one found in the Prophet VS.

The characteristic of this power supply is that it is fundamentally a high-performance switching power supply, but not directly connected to the mains voltage; instead, it is powered by a step-down transformer providing 18V AC or, better yet, 24V AC. Consequently, this power supply does not present the dangers inherent in using switching power supplies that are directly connected to the mains.

As a result, the overall efficiency of this power supply is much better than that of a purely linear supply. The 5V output comes exclusively from the switching power supply section, whereas the two analog-dedicated supplies, i.e., +12V and -12V, are derived from high-quality linear regulators, followed by filters to suppress any residual harmonics. The voltage supplied to the linear regulators is just above the input voltage required for their operation.

With all these precautions, the power supply runs globally very cool and is capable of delivering 1A on each of its outputs.

Additionally, a special connector provides everything a processor-based system needs in terms of RESET and faulty voltage indication, thanks to the addition of a specific component that performs monitoring and control operations with precision. This component is a MAX707CSA+T. Note that a CR2032 battery holder is available, providing a backup power pin on this connector.

Finally, three connectors — including one specific to 3.5-inch floppy disk drives — are provided to facilitate connections.

In fact, this power supply can be used both for repairing synthesizers, as in the case of the Prophet VS in this example, and for powering any device operating on 5V requiring high-quality symmetrical power supplies for an analog section.

A new batch of these power supplies has been produced.

 

 

 

 

 

The Z80 CTC: what a poem this thing is!

Over the past few days, I've returned to implementing the Drumulator in an FPGA. I won't go over the whole story again, but after multiple attempts and failures to produce a viable VHDL code for the Z80 CTC, I finally managed to create a 'minimal' version earlier this year (2026), thanks to a 'great' collaboration with AI that began in December 2025.

I knew that even if this time I managed to boot the Drumulator system on the Efinix FPGA board, my code wasn't very good—especially regarding clock domains, not to mention the rather poor operation of the entire channel clock management circuitry.

Confirmation that my 'CTC' wasn't working correctly came when I tried to implement the management of the Drumulator's data potentiometer."

The operation of this system is very simple to understand. The Drumulator initializes a pulse on the 74LS221 circuit. This pulse lasts for a 'certain time', corresponding to the charge of capacitor C77, charged by the current flowing through the potentiometer. This pulse acts as a gate, allowing the CLK.D clock to trigger one of the CTC counters — in this case, counter n°2, since it is connected to the CLK/TRG2 input.

However, this requires a specific programming of CTC channel 2, in counter mode. But that's not enough. The designers at EMU exploited the CTC's characteristics to the fullest. Thus, they fully utilized the operating behavior of the CTC's RESET system.

Last week, I completely rewrote the CTC code, this time fully managing the different clock domains and implementing the entire logistics chain for configuring the channel clocks. Apart from a small issue regarding the trigger edge of the Write signal, everything worked from the start.

But since the CTC is (in my opinion) now properly programmed, every little inaccuracy comes at a cost!

The first issue was initializing the counters to ZERO. I hadn't looked closely at the documentation on this point — well, because it didn't seem like the most important thing. Except that handling ZERO is important. In fact, it's very simple. The counter counts from 256 down to 0. Except that 0 triggers the counter reload and possibly the generation of the channel interrupt. The counter must therefore be 9 bits, not 8, and when you load the value 0x00, you actually need to load 0x100 — easy!

The other problem concerns the CTC's RESET system. Again, it's very simple once understood, but because it's not intuitive, it takes a little time to grasp how it works. It's a rather strange behavior — in any case, it doesn't match at all what one would expect from a 'standard' RESET. Since explaining it here would be a bit long, those who are curious can refer to the CTC documentation.

Since I now have a fairly good command of the Efinix debug tools, I was able to use them to trace the RESET behavior and finally understand where my misunderstanding lay. Now, it's understood."

And the result is:

The Drumulator is in tempo adjustment mode. This is done using the potentiometer stuck between the black and yellow terminals of the breadboard,

It works very well. However, on my breadboard, I powered the logic circuit not with 5V but with 3.3V. As a result, the trigger thresholds are no longer exactly the same. I was able to easily correct the operating range so that the minimum and maximum value ranges correspond correctly to the extreme positions of the potentiometer wiper, simply by adjusting the CLK.D clock that triggers counter n°2. 

Now I have all the technical aspects of the Drumulator implemented. I even have the metronome output! I don't think I will handle synchronization because everything is done via MIDI now. I'm also not going to implement the cassette interface since no one uses it. I'll consider using another backup system instead of the cassette.

I think I'll stop my FPGA-based investigations on the Drumulator for a while. Now I need to create an FPGA core for this Drumulator. I've started designing the printed circuit board. But before moving on to the physical realization of this circuit, I will now finalize the MSX cartridge. It is with this cartridge that I will see whether my Efinix FPGA implementation has been done correctly.

I've been tinkering with FPGAs for years. But I hadn't acquired the general mindset to adopt for programming them. AI was a very good trigger, showing me the way of what needed to be done and what was best to avoid. With this help, I accomplished in 4 months what I hadn't managed to do in over 10 years. Beyond the pleasure of (a small) success, it is also and above all the pleasure of the intellectual groundwork progression that this gave me!

MSX cartridge, it's progressing...

So this time I'm not really making progress in terms of building this MSX cartridge, but I'm tackling all the programming aspects of the future equipped cartridge, which therefore includes an Efinix Trion FPGA.

For now, I've implemented a fairly standard FPGA connector on the MSX cartridge. The problem is that I haven't really experimented with programming Efinix FPGAs using an external JTAG probe. I've simply planned what seems to be the minimum in terms of hardware and am doing all my tests using the JTAG probe on the Efinix development board.

So I got this type of JTAG programming board based on an FTDI 2232H component :

That's about 30 dollars!

Setting up this type of interface involves three steps, after which it will be configured as a JTAG probe by the Efinix programming software:

1.     Configure the hardware resources of the interface.
2.     Install the necessary Windows driver so that the 'new' interface is recognized.
3.     Establish connections with the FPGA's JTAG connector.

For step #1, it is necessary to modify the operating mode of the two ports (A & B) of the FTDI 2232 circuit. To do this, you need to download the FTprog software from the FTDI website, scan for FTDI-type USB interfaces, then configure the two ports as follows:

You just need to configure both ports A & B in 245 FIFO mode. The driver type does not need to be changed. You can also modify the string descriptor to have something more explicit displayed when the interface is detected in the Efinix software. In fact, and after several issues while figuring this out, I copied exactly the same information as that written in the JTAG interface of the development board. The key takeaway, at a minimum, is to configure ports A & B in 245 FIFO mode. 

And that's it. Never modify the VID and PID because after that it may become very complicated to make the FTDI component reachable again by 'standard' software. I had to find a utility on the Internet to perform a 'brute force' erase of the configuration EEPROM, which made it possible to find the interface again using the FTprog software.

For step #2, it is now necessary to modify the drivers for the two interfaces corresponding to ports A & B of the FTDI component. By default, both interfaces are configured with an FTDI driver. To change this configuration, you need to download and install the well-known Zadig utility. You can find documentation on the Internet about its use, which is very simple. At this point, you just need to replace the original drivers of both interfaces with the WinUSB driver. Do this for both interfaces. Because yes, it seems that the Efinix software prefers the JTAG interface to be set up on port B, but doesn't dislike the situation if port A is not also configured like port B. I have no explanation for this, but judging by the messages provided by the Efinix programming interface, I received 'blue' warning messages indicating that a JTAG interface was present on port A but that 'usually' or 'normally' (I'm not really sure), it's better to have it on port B of the 2232 chip. So be it!

I have already done the job, which is why the driver shown is already the WinUSB driver on the left side of the window. Initially, at this location, you will see the FTDI driver.

After these modifications, you will get the two interfaces shown like this in the devices:

'Trion T20 Development Board' is the information I entered into the new FT2232H chip using the FTprog software.

For step #3, All that remains is to connect this new JTAG interface to the Efinix development board. Nothing complicated, except that you still need to be careful about certain points that are not really detailed in the documentation.

The first point concerns the JTAG interface integrated into the development board. I haven't mentioned it until now, but I am using the T20 BGA 256 board. This board has a JTAG connector that is connected on one hand to the FTDI 2232H chip integrated into the board, and on the other hand directly to the FPGA's JTAG port. Since there cannot be two masters on board, you absolutely must disable the internal JTAG interface of the development board. The JTAG connector has a pin labeled 'FRST' which, as its name seems to indicate, stands for FtdiRST. Simply connect this pin to ground by connecting it to the ground pin located right next to it. 

Then, simply connect the classic JTAG signals, namely TMS, TCLK, TDI, and TDO, between the external JTAG probe and the JTAG connector of the development board, not forgetting to connect ground. And... it's almost done.

Yes, almost done, but not quite. In its current state, you will be able to use this external probe, which will be properly recognized by the Efinix programming software. You may even be able to read the FPGA's identification number on your board, but you will not be able to program it.

Because 'the funny thing' is that the Efinix software must temporarily put the FPGA into RESET before starting its programming. I searched through quite a few docs to find out why the Efinix programmer could successfully read the FPGA's ID but was unable to program it, and it took me a little while to find the answer.

Well, in fact, another pin of the FTDI chip is used to reset the FPGA: it's pin ADBUS4 of the 2232H. 

Follow the arrows.

The two points indicated by arrows need to be connected. The goal is to bring the ADBUS4 pin to 'the' available pin on the external JTAG connector. For your information, the JTAG interface I received is version V3.6, and you can find its schematic at this location: GitHub

I simply used a small piece of wire to connect these two points on the solder side. Once the board is put back in its case, this wire is unlikely to move or potentially break a solder joint.

 Simple, isn't it?

Following all these steps, simply summarized here but which actually took me quite some time, I was able to program the FPGA of the development board in JTAG mode without any issues. That was a good start. But you are certainly aware that while this allows the FPGA to be configured, it is a dynamic configuration stored in the FPGA's internal RAM. As soon as the FPGA is reset, it cannot find a configuration file because the external EEPROM has not been programmed. And you are also certainly aware that it is possible to program an external EEPROM connected to the FPGA via the JTAG port of the same FPGA. This is a specific programming mode that the Efinix software allows you to use.

The advantage of this system is that to be able to develop, meaning to quickly modify the FPGA's RAM, the JTAG interface does that, and once development is complete, it is also possible to program the final firmware into the EEPROM using the same JTAG interface. There is no need to provide an additional SPI interface to access the external EEPROM. 

So I programmed the Drumulator firmware, which I am still developing, into the EEPROM of this board using the JTAG port, and here is the result :
 

Better than a long speech: it works!

After these adventures, I now have all the elements to continue working on my MSX cartridge. However, I need to add the RESET pin to the JTAG connector because that is not the case for now.

If you have read this article, I hope you found it useful. Not that everything described here is complicated — and it isn't — but when you don't know about it, it's much less straightforward to grasp.

MSX cartridge, it's progressing...

On this cartridge, I'm at the stage of trying to create the PCB. In my last post on this subject, I was at the beginning of creating the PCB and I had absolutely no idea whether I would manage to make something clean. Well, now I have the answer: 

All the tracks are routed. I still have a bit of work to do on improving the routing, with no major functional impact — more about streamlining. While working, I switched to version 10 of KiCad. I've known KiCad for over 20 years. A lot of things have improved, but I feel that since it went into 'semi-professional' mode, there are ways of doing things that have more to do with professional software than with solutions accessible to the greatest number of people.

A small message to the KiCad developers: By all means, improve its operation and features, but don't turn it into a clone of professional solutions that require months of training and practice to create an amateur circuit. You're now moving a bit too far away from the accessibility that has made KiCad successful so far. As for me, I think I won't update KiCad any further, especially since dark theme is finally available with version 10.

Of course, I have absolutely no idea whether this board will work or not. This is my first implementation of an Efinix FPGA. But you have to start somewhere. And, as a result, this allows me to compare this type of FPGA with equivalent FPGAs from Gowin. While it's true that Gowin FPGAs are much more expensive than Efinix FPGAs, the 144-pin Gowin version equivalent to the Efinix version used here, requires far fewer external components to get it running and is, in my opinion, easier to implement on a circuit. The Gowin module I made worked fine with just a two-layer board. Here, I was forced to go with a four-layer board.

If this Efinix FPGA implementation works, I will nevertheless have a functional template for implementing the component. This will allow me to create more complex designs more easily in the future with these components. 

The Drumulator in a FPGA.

Might as well say it right away: it works.

And to specify what works: well, actually, everything!

That is to say, when I press the 'pads', I do get the correct sounds.

Quick summary of the background: a few years ago now, I decided to 'transfer' an entire Drumulator into an FPGA. Well, for the digital part, obviously.

And to be exhaustive, my adventures with FPGAs started a long time ago. I had stopped in 2014 with the integration of a Prophet VS's processor board inside an Altera FPGA. At that time, the work was relatively simple, since it involved assembling distinct IP blocks. But obviously, when it came to creating the missing components from scratch, that was a whole different story. I had to get into the 'hard' part of VHDL coding (the language I primarily use). So I had chosen to start with what seemed to me at the time to be a simpler machine than the Prophet VS, namely the Drumulator.

In reality, it wasn't any simpler. There too, everything went very well as long as I emulated the Zilog CTC with a super simple interrupt generator that actually simulated the operation of the vectorized interrupt system. Obviously, that wasn't going to be enough because the CTC generates multiple interrupts, so it was absolutely necessary to manage the Z80's vectorized interrupt system.

It was from that moment that the troubles started again. I had to once again confront VHDL.

The fact is, I have no formal training in the subject, to begin with. Doing logic isn't very complicated, but switching to the formalism of a hardware description language like VHDL requires an 'approach' that I didn't have. Basically, I didn't know where to start to truly get into this subject.

And that's when AI allowed me to do it. In fact, I used it as a teacher. Now obviously, I knew a bit of VHDL, which helped me a lot. As for the AI, I had at my disposal a teacher who never got tired of answering, had answers to almost everything, was available 24/7, and practiced no form of social class discrimination, and therefore no filtering in the acquisition of knowledge. Which is obviously contrary to what I experienced throughout my schooling in France, since this country practices social discrimination endemically. Coming from the very bottom layer of French society, I had no chance of accessing anything remotely advanced in electronics. The French education system respected its social objective to the letter.

AI therefore allowed me to bypass this system and, assuming I possess at least the minimum capacity to level up, with the training provided by AI, I managed in three or four months to get past a major hurdle.

I close this parenthesis with this magnificent image of the development system used for my FPGA work:

So, for now, I haven't implemented an analog output multiplexing system. The Drumulator uses the time switching principle to generate its eight voices. Each output is reconstructed by an operational amplifier followed by its small holding capacitor. Very standard. Except that I'm using serial buses to manage this whole system. The DAC is not a parallel data bus DAC but works using an SPI bus. The same goes for the final volume control circuit and the final audio channel switching.

Moreover, the sequencing system that generates the sound waves works in a fully pipelined manner. Managing the other serial buses will be done by adding stages to this pipeline. The only thing I paid attention to is that the circuits used are fast enough so that all the information has time to be transmitted between each new sample output.

The sound produced by my system is slightly different from the sound produced by the Drumulator. On one hand, I don't have the analog filtering system, and above all, I'm not reading the samples at the exact frequency of the Drumulator, and actually, I'm not entirely sure that the values used to translate the 8‑bit samples into 12 bits for the DAC are completely correct.

A few years ago, I implemented the Drumulator's sound generation system on an ARM processor, just to get familiar with the companding system it uses. I had manually calculated the conversion table based on the original component documentation. To go all the way,  this time I also asked the AI to calculate this table for me. I must admit the result is quite convincing.

To illustrate all this, I'll try to make a short video with sound...

MSX Cartridge.

Some months ago now, I decided to create a cartridge for MSX computers. I wasn't really sure which direction to take. I tried to keep it simple by using a fast processor, but the various tests I carried out yielded no reliable results.

So I ended up facing a dilemma: use a specialized processor like the Raspberry Pi Pico, or go with what seems quite inevitable to me, namely the use of an FPGA.

I don't appreciate Microsoft applications at all for a whole host of reasons, yet the most serious way to work on the Pico involves installing the necessary development environment within Visual Studio Code. Well, I'll never manage that. I just have to open the Microsoft application to be faced with all sorts of acronyms and logos, the kind I find on my washing machine, but in an A320 cockpit version, and I nearly keel over from sheer exhaustion.

So I chose a different approach, even though it's not the same thing at all. This time, I'm going with an FPGA. The advantage is that I can have more FLASH and SRAM memory to create my cartridge since I'm not constrained by the Pi Pico's internal resources. Furthermore, the FPGA will have a fast internal processor allowing me to manage the overall operation of the cartridge.

So yes, I prefer to challenge my brain with rewarding things, like learning VHDL and the whole Efinix FPGA environment, rather than constraining it with a vision of the Microsoft kind that holds no interest whatsoever.

As a result, the circuit I plan to build bears no resemblance to the early circuits and is far more complex. After doing a rough layout, I contacted specialists for the actual production of the circuit. The price is inevitably very high for this kind of 'personal DIY project', even more so in France. So, I still tried to see if I could manage to do something with my limited experience in the subject. This brings me to this result:

For now, I have absolutely no idea if I'll succeed in routing this circuit. In the past, I did the same kind of work on GoWin FPGAs, but it wasn't as difficult. The Efinix FPGA requires more external resources for its implementation.

After embarking on the adventure with Efinix FPGAs, particularly regarding the use of Efinix's internal soft processor, I must say I was on the flat. Now, the path is starting to get seriously steep...

Efinix FPGA, Gusmanb Logic Analyser.

I have been experimenting with Efinix's development tools for several weeks now. Apart from the fact that overall I find these tools quite well-designed, efficient, and easy to use, the fact remains that some things don't seem very practical to me.

I replaced the built-in code editor with an external editor, namely Zed, which has a plugin for VHDL syntax highlighting. Because with the habits and automatic reflexes that develop, juggling the window parenting system of Windows becomes very unbearable very quickly, just like Windows itself, actually.
Once Zed was adopted, development with the Efinix tools became fluid and productive.

Another point to mention, but here I am issuing a warning. It might indeed be that I don't possess enough knowledge to use the integrated debugging tools properly. The fact remains that the internal Efinix logic analyzer always starts from the clock root to manage its sampling frequency, and always uses a clock source from the design as a reference. I haven't yet found a solution to sample at an arbitrary clock value. And I don't even know if it's possible. No, I haven't read all the documentation. But that's beside the point anyway.

The 'thing' is that it's relatively difficult to sample low-frequency signals. Which is the case for a serial link at 19200 x 16 baud. So, how can one practically verify the signal shape on a transmission pin?
Because now that I have managed to implement the transmission and reception for a ZILOG SIO, before continuing with the implementation of functions, I first need to verify that the various formats are correctly respected. That is to say, the parity and the number of STOP bits.

The ideal in this case is obviously to have an external analyzer. I do own one, but I never managed to get used to its PC interface, and I don't find it very easy to use. Especially since it is limited in channels and recording buffer size.

A few months ago, I came across a YouTube video presenting a logic analyzer based on a Raspberry Pico circuit. The project seemed to be progressing well until it hit the famous 'bug' in this circuit's IO ports. Then, I went back to look at the project when the Pico 2 circuit was released. The project had evolved to use this new component. It had reached the stage of proposing a printed circuit board containing all the necessary elements to serve as a 24-channel logic analyzer. Well, 24 is 16 + 8. This is precisely why all professional suppliers will never release hardware with this number of channels. Indeed, this number represents the amount required to be able to trace the bus of a standard 8-bit processor. Therefore, professionals will provide 16-channel devices at a 'reasonable' price with mediocre graphical interfaces, offering you to upgrade to the 32-channel version at a much higher cost. This commercial practice is 'rotten' in the medium term. Because, at some point or another, a 'heretic' will release hardware at a ridiculously low cost that will break this strategy.
And the 'heretic' in this case is Agustín Gimenez Bernad. This gentleman has developed a 24-channel logic analyzer, information for which you can find at this location: https://github.com/usmanb/logicanalyzer

As for me, I didn't even try to build the hardware. I found a ready-to-use circuit on AliExpress at the incredible price of €28 (03/2026). In fact, I acquired two units because, as if that wasn't enough, two circuits (or more, it seems) can be chained together to increase the number of channels. I haven't tried that yet.

The software is also found on the GitHub repository. In my case, I downloaded version 6.0. Knowing that the software also has a large number of decoding 'plugins', it is necessary to install Python to take advantage of them. The only small restriction is that the Python version must be 3.13 maximum. The current version is 3.14 (03/2026), but previous versions are still readily available without issue. 

In a word, this system, on paper, seems to tick all the usability boxes for me. And, with the SIO development underway, this is the perfect time to try out this logic analyzer.
Here is what the capture of the serial frame I send from the FPGA at system startup looks like. With the UART decoding configured, it's an absolute child's play to not only follow all the ASCII codes in the frame, but also, and most importantly, to visualize the effect of the parity configuration and the number of stop bits.

And so concludes the description of the process that led me to use this analyzer. Yes, because the whole thing is so well-made that starting it up is almost knowing how to use it. One or two tries and you've got it. The 'thing' is so simple, intuitive, and powerful that I have nothing else to write. Simply magic!

This brings me to a small point about the tools used to make the development of my FPGA projects easier:

• Zed, for easy editing of FPGA, C, and other sources.
• GTKWave for easy visualization of signals produced by the Efinix logic analyzer.
• Agustín Gimenez Bernad's (magic) logic analyzer.

The cost of all these tools combined is practically zero, since only the logic analyzer hardware needs to be considered, and it is extremely low.

There are solutions under Linux, but for now I haven't switched to that OS. I used it for a very long time, but until now, only the Windows system allows for reasonably consistent updates of the system and tools. Which is not the case with Linux. And since I hate wasting time on things that aren't properly managed, well, following update troubles under Linux, I stopped working with this system suited either for computer gurus or basic secretaries, but certainly not for people like me. Unless I switch to Mac, ultimately the most reliable Linux on the market ;-)
 

Cody the Computer and Its Keyboard.

A few months ago, I presented Frederick John Milens' initiative to build a small computer in the purest style of the 80s, closely resembling the Commodore 64.

https://www.codycomputer.org/

Since then, the new version of the Commodore 64, the Commodore 64 Ultimate, has been delivered by the brand new entity Commodore.net.

What differentiates Frederick's version is that his creation uses 'real' physical components, even though the video and sound functions, among others, are handled by a Propeller processor. His concept, although not advertised as C64 compatible, nevertheless remains exactly the same style of computer as the original C64.

The version created by the new Commodore entity, for its part, is based on an FPGA design. It is not my intention to prefer one version over the other. Both are interesting. I received the latest C64 and also built a copy of the Cody.

https://www.commodore.net/

Beyond the hardware work, Frederick has done a significant amount of documentation. In fact, the book available in PDF on his website makes it possible to understand absolutely all the hardware aspects of his machine. Additionally, his GitHub repository provides absolutely all the information necessary to build the machine yourself.

As far as I'm concerned, I have only one small criticism of his approach. It concerns the keyboard. I don't see anything interesting about building a keyboard yourself. Unless, of course, it's a very special keyboard like a processor board with a hex keypad. Otherwise, I prefer to use a standard USB keyboard, and besides, it costs less. However, the USB output of the keyboard obviously needs to be adapted. I've already built this type of interface in the past for an MSX machine. On the other hand, I'm not a fan of interfacing with the original input/output port. There can sometimes be synchronization issues.

So what to do for Cody? Well, since all the resources are available on Frederick's GitHub page (Github), I decided to try a different approach, which is to directly provide the received keyboard code onto the processor's data bus. 

For this, I created a small adapter printed circuit board that I will place on the I/O interface circuit socket. It will contain the interface circuit plus the connection to a small external board designed to provide a serial output corresponding to the key codes typed on the USB keyboard.

There's also the video output, which is a bit too 'retro' for my taste, but there are inexpensive converters for this type of video output to VGA. So, I'll maybe look into that later. Since I have put together VHDL resources for creating a relatively universal frame-buffer, I might be able to use these resources as part of the Cody project.