How to go on vacation with peace of mind!

I would simply say: with as few nagging concerns as possible. 

And the best way to achieve that is to finalize certain projects that are at a conclusive stage. 

Since December 2025, I've been working on two main subjects: an FPGA-based Drumulator emulator, and porting an MSX cartridge design to FPGA. Both have been important because, first, I really had to level up my VHDL skills. Implementing the ZILOG CTC controller in VHDL — complete with the full vectorized interrupt system — was a genuine challenge. But without it, I couldn't have implemented even the Drumulator's Data potentiometer. 

That's the software side of things. 

On the hardware side, I also had to design a PCB for the MSX cartridge, this time for the larger FPGA — an Efinix TRION T20. And that meant tackling my very first four-layer PCB design.

What's more, TRION FPGAs are somewhat trickier to implement than Gowin FPGAs, for instance. That said, it really depends on the specific chips and other factors that can certainly nuance that view — but for this MSX cartridge, it definitely held true. With the physical space constraints of a cartridge, plus the fpga size and the number of passive components needed, sticking to two layers was simply out of the question.

I actually reached out to a PCB specialist who quoted me over €1,500 just for the design work. No doubt he was a pro, but that was way out of my budget — even when considering more affordable options from Asia.

So I had no choice but to tackle it myself!

It took a fair amount of time to lay out the board in KiCad, assemble it, and start testing. But at least I had the satisfaction of seeing the FPGA communicate with the JTAG probe almost right away.

After that came the implementation of the internal Sapphire processor, and finally the interfacing with the MSX bus.

A professional would say none of this is particularly remarkable. And I'd agree. But when you're a weekend hobbyist with no formal background in the field, the road is obviously a bit less 'smooth sailing.'

But there it is! I finally got my first MSX machine to boot on my new cartridge. And I have to say — it makes me absolutely thrilled!

It took a few hours of work just to be able to take this photo — and then I had to adapt the VHDL code I'd written during my tests with the Efinix development board to this new hardware. Unsurprisingly, it didn't work straight away, but thanks to Efinix's debugging tools, I finally managed to get the cartridge up and running:

In step '1', the MSX computer places address addr_IN = 0x4000 on the bus. This is the first address where a valid cartridge signature is expected. In step '2', the MSX reads from the cartridge with SLTSL_IN = 0 AND RD_IN = 0, and finally in step '3', the cartridge returns 0x4241 — which is the signature, i.e. 'A' and 'B' in ASCII.

You may notice that in step '2', the address used to access the internal FLASH on the cartridge is not 0x4000 but 0x2000. That's simply because the FLASH has a 16-bit data bus. Bit '0' of the MSX address is ultimately used to select which of the two bytes should be presented on its data bus. This is also why the FLASH returns 0x4241 — both bytes are read out as a single 16-bit word.

So, a bit of internal address translation going on.

I should also mention that during my initial tests, I used small delays to handle FLASH writes. These aren't standard components — writing to them requires a specific procedure and wait times. To keep it short, this time I'm using the FLASH's #READY/BUSY signal directly for all operations, so I'm getting as close as possible to the FLASH's maximum speed. And I have to say, writing — and thus transferring data from the PC — is now significantly faster.

From time to time, I also work on other little projects — like the CODY computer, for instance.  

I just find this tiny machine really interesting and very affordable, and since all the sources are available, it's a great source of creative fun and distraction that brings me back to my 80s computing pleasures. And that's precisely what this little computer is all about. So I adapted a USB keyboard adapter for it.

I used a solution that could definitely be improved, especially by using a Pi PICO. And since I've just managed to get the PICO development environment up and running, I think I'll do a little study on replacing it with that chip.

Finally, I was able to type things on the keyboard and run the first little program that works.
 

I also sent out a USB expansion board for an AKAI sampler to be fabricated. I honestly have no idea whether it'll work, because Akai used some pretty odd tricks on their original board. But at least this time, the backplane connector should be correctly wired — because despite double-checking everything, I still managed to reverse the ROWs. So the whole thing was upside down. You don't get to be a "Sunday tinkerer" for nothing!

I should get the board back when I return from vacation. I'll still have a few days to test it. And if it doesn't work — well, so be it. I'll have done what I could with this board and Akai's rather baroque design choices.

December 2025 was a big month for me. That's when I really started picking at artificial intelligence about VHDL, and it helped me make huge strides on the subject.

But beyond the technical side and the knowledge I gained, what really mattered was the freedom to learn. 
I don't know how things work in other countries, but Western societies tend to be pretty rigidly class-based. France is a perfect example — it still runs on a kind of "Ancien Régime" model where, if you're a nobody (which I am), you're effectively locked out of higher education. I'm oversimplifying, but the core truth is there: the education system is basically a class-filtering machine that only lets the upper classes access the kind of studies that lead to a "normal" professional life.

"The big shots land the fancy seats
Right on
The rest get Saint-Maur, Châteauroux Palace
Nowhere to go"

(Saint-Maur and Châteauroux are prisons, for real.)

InFrench original : 

"Les cadors on les retrouve aux belles places
Nickel
Les autres, c'est Saint-Maur, Châteauroux Palace
Plus d'ciel"

(Song by Alain Souchon ‧ 1988)

Artificial intelligence currently lets you break out of that situation. Which is a huge pleasure for me, because it makes me more creative. But for how long? That's a whole other debate.

Msx Cartridge, first run.

The MSX cartridge saga continues...

As a reminder, here is what the cartridge should look like once finished. I had the printed circuit board manufactured with a request to have all passive components in 402 packages placed, because doing that by hand: why not, but actually, no!

On the other hand, I had to solder the FPGA myself. Even though it's a 144-pin package, this type of package is very easy to solder. I've already had the opportunity to do it before; a little practice is enough to carry out the operation without difficulty. I also asked for the flash to be placed on the board.

The FPGA functionality tests did not reveal any particular design issues. I just had to remove a resistor on one of the JTAG signals — a useless resistor that I had added without much thought on my original schematic.

The first programming of the FPGA therefore went without a hitch — see previous articles for more details. The famous 'Hello World' worked on the very first try.

So the next step was to program the Sapphire RISC-V processor core provided by Efinix into the FPGA, in order to implement the whole file-reception program from the PC, as well as the routine to write that file to the Flash.

When I do feasibility tests, the code I write is never very clean. Rewriting it for the final implementation allows me to follow a cleaner structure.

To check that the application code for the processor was starting to work properly, I simply programmed the UART for communication with the PC, the processor's internal timer to generate a one-second interrupt, and the timer interrupt routine to send a CRC-16 character (actually the character 'C') to the PC. Indeed, it's upon receiving this character that the Ymodem transfer protocol can start transmitting.

Because, no, I'm not using the Windows copy-paste file system over USB media. That system isn't designed to be controlled — it either works or it doesn't, with no visibility. So I preferred a more controllable transfer method.

And that's when the real trouble began. Although the code running on the processor started correctly and displayed the program prompt along with a few occurrences of the CRC-16 character, the program would stop without any intervention from me.

For a main loop consisting of while(1); that's a problem.

So I spent an evening eliminating possible causes for this malfunction. Then I remembered a small electrical issue I'd encountered during my initial tests a few months ago — a minor problem with ground loops and/or noise. This issue was obviously causing disturbances on the JTAG link, which in turn would crash the processor.

I inserted a USB isolator dongle on the USB hub and plugged the JTAG dongle into it.

And this time, no more problems. The processor runs its program without any issue.

So, my very first 4-layer PCB I designed, even if it's not the pinnacle of the art in this field, isn't causing any issues so far. The code I developed on the Efinix evaluation board works as well. Up until now, the most complex systems I had produced were circuits around Gowin FPGAs, which are simpler to implement. For this MSX cartridge, the whole circuit is nevertheless a bit more complex.

I must say I'm quite pleased with the result :

The Cody Computer : With an USB keyboard?

From time to time, I've mentioned the little computer designed by Frederick John Milens. The main reason for my interest in this small machine is that all the source code is provided, it's very simple to build, and for learning what microcomputing is, or what it was, or what it might well become again, it's an absolutely brilliant tool.

I repeat myself, but for me, the only "small issue" with this machine is its keyboard. In my opinion, it's really not very practical, and it adds an unnecessary extra cost to its construction.

So much so that I didn't actually build the keyboard. As a result, in the few months I've owned this little computer, I've never been able to type anything on the keyboard to test its functionality. Until now, I only had its startup screen. That's already a good sign that it's working, but still, a bit frustrating.

So, a few months ago, I developed a small electronic board to adapt a standard USB keyboard to the Coddy. For the interface, two approaches are possible. The first is to connect directly to the keyboard connector, thus simulating the keyboard hardware with I/O ports on a microcontroller.

This principle works, but obviously, since the computer's keyboard scanning and the microcontroller's I/O matrix scanning are asynchronous, there are rare occasions where a key press is missed.

The other solution is to present to the computer, one way or another, the key code directly returned by the USB keyboard. But this solution, although more reliable than the first, requires having full access to the computer's resources, because it involves not only some hardware modifications but also system software changes.

Since the designer of this computer provides absolutely all the source code, I opted for this second solution.

The hardware principle used is simple: a USB-to-serial converter translates the codes from a standard USB keyboard into codes available on a serial port. A small microcontroller retrieves these serial codes and presents them in parallel on the computer's data bus.

A tri-state buffer allows placing this code on the data bus using an additional selection signal generated from the Coddy's VIA selection signal, discriminated from the VIA by taking into account an extra address signal. Basically, I'm using one of the VIA's memory maps to place the I/O registers that provide the keyboard code.

And that's it.

From a software perspective, it's "simply" a matter of hooking into the existing system code by adapting certain routines according to the new hardware.

Said like that, it sounds simple, but in fact it's not really, because even though all the source code is available, you still need to understand how it works and its subtleties. And adapt to the 6502 assembly language, which I had never used since until now I've always worked on Z80 or 68000. This caused me some initial confusion. But then again, when you know assembly language, switching from one processor to another isn't difficult.

And so, after a few hours of studying and testing, I finally have a keyboard connected to the Coddy. 

And, compared to my previous article where I showed the very first signs of character reception but where the whole processing of commands entered via the keyboard was not yet functional, now it is fully working.

And now?

Well, not everything is actually functional. The "break" that allows stopping a running program hasn't been implemented yet. This system uses certain hardware lines from the original matrix keyboard to generate the Break. I haven't implemented it for now. After the few hours I spent on the BASIC assembly source, I don't think it will be very complicated to implement.

My interface is a bit complicated. I use a small USB-to-serial conversion module, then my decoding and data presentation board that interfaces with the Coddy's data bus.
I think there's a way to do it much more efficiently by using a Pi Pico with the TinyUSB library.

Since I managed to set up (without difficulty) the Pi Pico development environment with Visual Studio Code, I should be able to greatly simplify all this into something better!

And yes... Unlike my first attempts at installing Visual Studio Code with the Pi Pico package for VSC, I was able to complete the installation without any problem whatsoever. It just goes to show that some Microsoft solutions work almost intuitively!

And I almost forgot to thank Frederik for a very handy little detail in his code: PUTHEX.
This routine allows displaying in hexadecimal at the cursor position any data previously placed in the A accumulator.
A very handy little utility for real-time debugging.

 

Some headway despite the heatwave.

Despite this intense heat, I managed to make some progress on my developments. And to kick things off, a magnificent failure. Well, it's still progress, I suppose. This concerns the USB expansion board for the Akai S5000/S6000 sampler. My first prototype doesn't work at all. Mind you, that does make it easier to find the cause. I did indeed make a beginner's mistake on the PCB. It's so obvious, even though I checked my schematic several times, that I'm simply not going to reveal it. So I've corrected my circuit. Now I just need to get it re-fabricated.

There's no visible difference on this new board, except that I've moved the USB-C connector out a bit more, because once the current board is installed in the sampler, I realized it was missing just a tiny millimeter to properly plug in an external cable.

Luckily, I do have some genuine progress to report, particularly with the MSX cartridge. I won't recount the whole development story of this project here, but suffice it to say that I recently moved over to FPGA. For that purpose, I switched to an Efinix TRION FPGA. These FPGAs are new to me and are a little trickier to implement than the GoWin FPGAs I used before, but they're also less expensive.

Given the tight space constraints of an MSX cartridge, and since I'm using a 144-pin device, I had to opt for a four-layer PCB. The first spin of this board isn't perfect, but it's still well enough laid out to allow programming the FPGA through its JTAG port.

The image below shows the result of programming the FPGA via JTAG. In reality, it's a little more involved than that. Using the JTAG interface alone, you can program the FPGA's internal RAM 'on the fly'—which is great for development. However, it also means that whenever the FPGA is reset or powered off for any reason, that RAM is wiped, and the FPGA then expects to find an external EEPROM holding the configuration bitstream to reload its internal RAM and boot up. This is called SPI ACTIVE mode, because the FPGA itself initiates and manages the copying process from the external EEPROM.

So how do you program that EEPROM when you haven't added a dedicated connector for an external SPI programmer? The answer is simply to use 'SPI over JTAG' mode. And that's where the magic happens. During programming, the bitstream is written directly into the SPI EEPROM through the JTAG port. Once that's done, a simple reset of the FPGA is all it takes for it to fetch its configuration from the EEPROM—and that's exactly what this image illustrates.

Here's what my development setup looks like:

I should also mention that to program this FPGA, I'm using a commercial interface I bought myself on Aliexpress JTAG probe. Although it comes with the FTDI chip, it doesn't quite meet the specific requirements for programming the Efinix FPGA. One signal is missing from the output connector, but luckily that signal is available on the internal connector on the PCB. You just have to route that signal to the external connector, and the interface works flawlessly in JTAG mode with the Efinix programming software.

View of the programmer interface:

I'm quite pleased to have gotten this far from the initial study I did on an Efinix test board. It feels like years have passed since my successful tests back in December 2025, even though it's only been just over six months. Since then, I've made a lot of progress with VHDL and have other developments underway. Needless to say, I'm once again having to go back to the drawing board when it comes to implementing the Drumulator in FPGA. Plus, with the constraint I've imposed on myself to use as few American components as possible—would that force me to find other solutions? No, it encourages me to do so. And this constraint actually opens up potentially more interesting avenues. I have a few tests to run regarding the digital-to-analog conversion of the Drumulator, and I hope to be able to decide on the new direction to take based on the results of those tests.

My MSX development system in December 2025:

Despite a few hiccups that come with electronics development—especially since I'm more of a weekend hobbyist than a fully certified engineer—I'm pretty happy with the result. But still, I feel it's not going as fast as I'd like. I hope to ramp up my efficiency over the coming months.

Today's thought: US tariffs applied to France. Thank you, Donald Trump.

Today's reflection: US customs duties.

I really enjoy retro-computing. The question I hadn't really settled until now was: with retro components or with modern components? After the Z80 disappeared, the only 8-bit family left was the 6502, still manufactured by Western Design Center (WDC).

I'm currently spending some of my free time on the little Cody computer and the Memo-1, both based on the W65C02S from WDC. On the other hand, I also took an interest in the Commander X16, also based on the W65C02S, because I found that machine interesting.

To keep going with the subject and especially to build the Memo-1 board, I just placed an order for a few W65C02S processors and peripheral circuits from Mouser.

And this morning, the big surprise. Between the shipping costs and the taxes already paid, which already came to €28 for a total component price of €67.35—i.e., fees equivalent to 41.5% of the product amount—UPS has just billed me €49.14 in customs duties. The total fees for this order therefore amount to €77.14, or 114.53% of the value of the goods.

To be perfectly clear about that last sentence: I paid €77.14 in shipping, taxes, and customs fees for a component total of €67.35.

This is quite simply armed robbery. That reminds me exactly of Apple's business practices, which is why I have never bought any Apple products.

- My decision is simple: components of this kind from the United States—It's over.
- Retro-computing with retro components—It's over.
Period.

Americans are definitely no longer my friends!

Thanks to whom?
Thanks, Donald! 

Memo-1

In the series "other distracting activities during the heatwave," I looked into the very simple development by a "local guy"—that is, a Frenchman—who created a small computer based on the 6502 processor, with the particularity of being able to connect to the French Minitel. I always appreciate seeing this precursor of networked computing, the Minitel, being put to use. The capabilities of this machine were very limited. The major consequence was that for more than fifteen years, very simple and highly standardized "digital" applications were developed, which enabled French businesses to rapidly increase their efficiency. Imagine: a very simple interface whose learning curve—just a few dozen minutes—was enough to acquire the reflexes needed for a significant boost in usage efficiency. No stress for the user, the "graphical" interface never introduced any uncertainty. And what about security? Point-to-point connections with no possibility of hacking, unless one broke into Transpac distribution points, which were moreover equipped with non-standard hardware to even attempt sniffing a communication. How things have changed. Using Microsoft's online typewriter, um... yes... why not! And will this still be useful with AI?

I suggest you take a quick look at his YouTube page: Memo-1

I grabbed a few screenshots from his YouTube page.

Charming little board, isn't it?

As usual, its format is proprietary. The author took as an example the format of the old cardboard programming cards that were found on virtually all programmable computers of the era, notably the 80-column IBM cards. The problem with all these cards in incompatible formats is that once the board is assembled and tested, well, you put it away and move on... to the next one. As a result, you accumulate these boards and end up forgetting about them. And when you take them out of the drawers again, you still have to find or rediscover the specific connectors, the power supply, the USB-to-serial converter, etc.

So, for the past few months now, I have decided to take the boards I found interesting and remake them in the Euro RACK format. That way, it will "just" be a matter of getting a RACK with a backplane board and a standard power supply, and the boards can be inserted into the available slots, remaining easily accessible at all times, and, of course, stored in the same place. I have always found the TI99/4A's bus expansion system particularly interesting.

Gorgeous!

So I took the MEMO‑1 schematic and redrew it, replacing the expansion connector with a backplane bus connector. I also added a real‑time clock connected to the VIA via the I²C bus, which will need to be implemented using the VIA's I/O ports. This will require some specific programming that can be done later. As for the backplane bus pinout, I adopted the EuroBEEB format, since that system also used a 6502. This results in a board that is fairly easy to build and has a compact form factor.
 

On the original MEMO‑1 system, the expansion connector is designed to accept a cartridge. This will obviously not be possible with the backplane bus. It will therefore be necessary to design another small board that brings the essential signals to the front face of the rack, fitted with a cartridge connector. 

Regarding the Cody computer, which I also mention in this blog, I intend to convert it to a rack format as well. Since Cody has even fewer components, this shouldn't be very difficult, even if I incorporate the USB keyboard adapter.

These two systems, as well as the EuroBEEB board, are all based on the 6502, or its more modern version, still available from the Western Design Center. For now, I have nothing planned based on the Z80 processor, since it is no longer in production. However, since I have used Z80 cores in FPGAs in the past, I might be able to perform the same kind of conversion for Sergey Kiselev's CP/M-compatible board : Easy_z80 .

CODY computer

Between two "high-tech" developments, back to pure 80s style. This is about adapting a USB keyboard to the computer developed by Frederick John Milens, which I have already mentioned on this blog.

And no, for now I haven't done anything at all with this machine. I just built one copy because I think the whole package created by Frederick is absolutely brilliant. And I mean it. For anyone who wants to acquire the basics of digital electronics and fundamental computing, the machine, along with its documentation, is absolutely brilliant.

Moreover, the creator of Cody uses a whole ecosystem that is easy to get to grips with and completely free. Since all the sources are provided on GitHub, it is relatively easy to modify all or part of the design. And that is what I am going to present here.

As for me, I did not build the machine's keyboard. It is an extra cost and I prefer to use a basic USB keyboard. This is a purely personal choice. I am not interested in taking the retro concept all the way to the end. For me, the spirit matters above all.

So, to adapt a USB keyboard to this machine, the tactic I use is that of the cuckoo. Yes, the one that steals other birds' nests to build its own.

The idea is therefore to slightly modify the computer's hardware as well as the software that runs the machine. 

The concept of my build is very simple.
I use a USB keyboard to serial port converter module.
I use a small processor to convert this serial code into parallel code, which I then present on the Cody's data bus using a bus driver circuit. 

I am modifying Frederick's BASIC, written in 6502 assembly, to take into account not the scanning of its matrix keyboard, but rather the data coming from my small adapter board. Since the source is well documented, it is easy to make this type of modification. Although I have never used 6502 assembly before, I must say it is incredibly simple, even compared to the Z80. I am using TASM to assemble the source.

My system.

There are no modifications to be made in the Cody SPIN source, because the VIA that normally handles the keyboard matrix has a 256-byte address range, whereas only 16 are actually used. So I took bit A4 of the address bus to differentiate between an access to the VIA or to my board. This is the only physical modification I made.

In the ASM 6502 source, I added a constant representing the base address of my board. From then on, the function that retrieves a valid key code from the matrix keyboard boils down to:

KEYDECODE LDA KBD_CTRL     ; Reads the controller output into A
                         STA KEYCODE        ; Stores A into KEYCODE
                         RTS

Moreover, the KEYTOCHR function no longer does anything and returns immediately since there is no code conversion to perform, as I am doing this conversion directly on my small processor board.

Note that since I don't really know how the two special modifier keys are used, I may have to modify my system accordingly. 

But for now, this is enough for me to validate that my setup works.

The final procedure therefore consists, from a software standpoint, of assembling the BASIC source using TASM, recompiling the Cody SPIN project using Parallax's Propeller Tool, and loading the result into the Cody board. What's great about the Propeller chip is that all tests can be run in RAM, before saving the final code to EEPROM. Parallax's tool is remarkably easy to use.

I am using a RISC-V processor and its associated development IDE, MounRiver Studio. I have completed a number of projects with these tools and I must say that the latest version of the IDE is even more efficient, practical, and pleasant to use. In short, I don't regret the time I spent a few years ago discovering these processors.

Anyway, once everything is set up, it is fairly easy to achieve the expected result. I only spent a few hours of pure hobby time developing this adapter.

Validation of my concept.

And there you have it, the basics are working. All that remains for me to do is to complete the software part to fully emulate the original keyboard.

I really don't know where I'm going with this!

Implementing an FPGA isn't very complicated in itself. Whether on the hardware or software side, all it 'takes' is the right learning and a little (or a lot of) motivation to get there. No, it's rather what comes after that gets tricky. The potential of these types of circuits is so vast that you can consider using them in a huge number of applications. The problem then boils down to development cost. It's tempting to pack as much logic as possible into the FPGA. As a result, you quickly find yourself needing a chip with a good number of I/Os, and therefore a large pin count — and thus, a BGA package.

The development cost of a PCB designed to host a BGA-packaged FPGA is not the same as that of a board equipped with a small microcontroller. Nor are the risks of malfunction.

Considering that my field is more on the 'mixed' side — that is, both digital logic and analog — I find it risky to dive into the design of large PCBs containing a BGA package. I prefer to go the module route. That is, to focus specific efforts on the most precise sub-assemblies possible.

I'll take my process of putting the Drumulator into an FPGA as an example. Designing a relatively large PCB with a BGA seems inappropriate for an amateur-style build. So I decided to create an FPGA module tailored to my needs. I should mention that I've already built this kind of module with GoWin FPGAs, but in a 144-pin package. As a result, I didn't implement any memory on that module at all. However, with the goal of providing a complete computing core, I need memory.

So I went with an implementation using a TRION FPGA coupled with static RAM, an EEPROM for storage, a real-time clock, and a battery for backing up the memory and time.

Obviously, I couldn't get away with a two-layer PCB this time. This time, it's four layers. To keep manufacturing costs acceptable, I'm also forced to use through-hole vias, which complicates the board design.

But anyway, after a certain amount of time, I managed to produce the design for the board I want to build.

 

I have to admit that it took me a while to route the entire board. I think I've done a better job than I did with the MSX cartridge. I suppose that's normal — it takes experience, and experience only comes through iteration.

That said, on this board, I paid particular attention to the connections between the FPGA and the SRAM. The traces are short, and I matched the lengths of all bus signals, so that a fairly high operating frequency can be used.

As for the available I/O connectors, generally speaking, the traces on the 'component' side will be fairly fast since they won't encounter any vias. That should compensate for the signal integrity loss caused by longer trace lengths. The other signals will have at least one via along the path, and some of them two, though the latter case is very rare.

I have no idea how I'm going to actually assemble this board. The PCB manufacturer I work with doesn't stock Efinix FPGAs. So either I find another supplier capable of assembling these FPGAs, or I mount them myself. In which case, I'll need to get a hot plate to solder the main components.

Moreover, I don't know whether the wiring as it stands will actually allow the JTAG programmer to work properly. To figure that out, I need to wait until I implement the MSX cartridge, so I can verify that the power supply I've set up is correctly matched to the FPGA, and that the JTAG connections are properly made.

So, designing this board has already been an adventure. I was really skeptical about whether I'd even get to the end of it. Assembling this board is going to be a new adventure. But hey, if I really want to move beyond the 'Sunday tinkerer' phase, I have to take it to the next level. And since I've now gained a good command of VHDL coding, I no longer have a choice — I have to go for it.

 

And now for something completely different!

While waiting to receive the printed circuit board for the MSX cartridge, I started working on making a compatible USB card for the AKAI S5000/S6000 samplers.

The reason is that I know someone who is developing a new version of AKSYS that works perfectly under Windows 10 & 11. It turns out that not all Akai S5/6000 machines were shipped with this card. That's a shame.

So I studied the card I own and looked into whether it might be possible to create a new version.

It turns out that it is.

On the one hand, a USB component compatible with the one on the original USB card still exists today. And on the other hand, I was able to retrieve the logic equations of the PAL chip that is on this card.

For now, these equations seem to be correct, since I was able to repair another original but faulty USB card using a GAL programmed with my equations. So I am hopeful that this will work, even though the decoding performed by the original PAL is quite unusual.

The card's schematic is also unusual. Without going into too much detail, some functions are implemented by first latching a kind of register — registers made out of resistors and capacitors.

In short, the read and write functions are not direct but require going through other operations first.

In any case, I have completed the schematic and then the PCB for this card :

So, I have no idea whether this new card will work or not. The only way is to test it and compare the signals with the original card if it doesn't work.

Next steps after the first tests....

New batch of triple output PSU, for not only the PROPHET-VS!

A few years ago, I developed a regulated power supply with three outputs: +5V, +12V, and -12V, primarily intended to replace the one found in the Prophet VS.

The characteristic of this power supply is that it is fundamentally a high-performance switching power supply, but not directly connected to the mains voltage; instead, it is powered by a step-down transformer providing 18V AC or, better yet, 24V AC. Consequently, this power supply does not present the dangers inherent in using switching power supplies that are directly connected to the mains.

As a result, the overall efficiency of this power supply is much better than that of a purely linear supply. The 5V output comes exclusively from the switching power supply section, whereas the two analog-dedicated supplies, i.e., +12V and -12V, are derived from high-quality linear regulators, followed by filters to suppress any residual harmonics. The voltage supplied to the linear regulators is just above the input voltage required for their operation.

With all these precautions, the power supply runs globally very cool and is capable of delivering 1A on each of its outputs.

Additionally, a special connector provides everything a processor-based system needs in terms of RESET and faulty voltage indication, thanks to the addition of a specific component that performs monitoring and control operations with precision. This component is a MAX707CSA+T. Note that a CR2032 battery holder is available, providing a backup power pin on this connector.

Finally, three connectors — including one specific to 3.5-inch floppy disk drives — are provided to facilitate connections.

In fact, this power supply can be used both for repairing synthesizers, as in the case of the Prophet VS in this example, and for powering any device operating on 5V requiring high-quality symmetrical power supplies for an analog section.

A new batch of these power supplies has been produced.

 

 

 

 

 

The Z80 CTC: what a poem this thing is!

Over the past few days, I've returned to implementing the Drumulator in an FPGA. I won't go over the whole story again, but after multiple attempts and failures to produce a viable VHDL code for the Z80 CTC, I finally managed to create a 'minimal' version earlier this year (2026), thanks to a 'great' collaboration with AI that began in December 2025.

I knew that even if this time I managed to boot the Drumulator system on the Efinix FPGA board, my code wasn't very good—especially regarding clock domains, not to mention the rather poor operation of the entire channel clock management circuitry.

Confirmation that my 'CTC' wasn't working correctly came when I tried to implement the management of the Drumulator's data potentiometer."

The operation of this system is very simple to understand. The Drumulator initializes a pulse on the 74LS221 circuit. This pulse lasts for a 'certain time', corresponding to the charge of capacitor C77, charged by the current flowing through the potentiometer. This pulse acts as a gate, allowing the CLK.D clock to trigger one of the CTC counters — in this case, counter n°2, since it is connected to the CLK/TRG2 input.

However, this requires a specific programming of CTC channel 2, in counter mode. But that's not enough. The designers at EMU exploited the CTC's characteristics to the fullest. Thus, they fully utilized the operating behavior of the CTC's RESET system.

Last week, I completely rewrote the CTC code, this time fully managing the different clock domains and implementing the entire logistics chain for configuring the channel clocks. Apart from a small issue regarding the trigger edge of the Write signal, everything worked from the start.

But since the CTC is (in my opinion) now properly programmed, every little inaccuracy comes at a cost!

The first issue was initializing the counters to ZERO. I hadn't looked closely at the documentation on this point — well, because it didn't seem like the most important thing. Except that handling ZERO is important. In fact, it's very simple. The counter counts from 256 down to 0. Except that 0 triggers the counter reload and possibly the generation of the channel interrupt. The counter must therefore be 9 bits, not 8, and when you load the value 0x00, you actually need to load 0x100 — easy!

The other problem concerns the CTC's RESET system. Again, it's very simple once understood, but because it's not intuitive, it takes a little time to grasp how it works. It's a rather strange behavior — in any case, it doesn't match at all what one would expect from a 'standard' RESET. Since explaining it here would be a bit long, those who are curious can refer to the CTC documentation.

Since I now have a fairly good command of the Efinix debug tools, I was able to use them to trace the RESET behavior and finally understand where my misunderstanding lay. Now, it's understood."

And the result is:

The Drumulator is in tempo adjustment mode. This is done using the potentiometer stuck between the black and yellow terminals of the breadboard,

It works very well. However, on my breadboard, I powered the logic circuit not with 5V but with 3.3V. As a result, the trigger thresholds are no longer exactly the same. I was able to easily correct the operating range so that the minimum and maximum value ranges correspond correctly to the extreme positions of the potentiometer wiper, simply by adjusting the CLK.D clock that triggers counter n°2. 

Now I have all the technical aspects of the Drumulator implemented. I even have the metronome output! I don't think I will handle synchronization because everything is done via MIDI now. I'm also not going to implement the cassette interface since no one uses it. I'll consider using another backup system instead of the cassette.

I think I'll stop my FPGA-based investigations on the Drumulator for a while. Now I need to create an FPGA core for this Drumulator. I've started designing the printed circuit board. But before moving on to the physical realization of this circuit, I will now finalize the MSX cartridge. It is with this cartridge that I will see whether my Efinix FPGA implementation has been done correctly.

I've been tinkering with FPGAs for years. But I hadn't acquired the general mindset to adopt for programming them. AI was a very good trigger, showing me the way of what needed to be done and what was best to avoid. With this help, I accomplished in 4 months what I hadn't managed to do in over 10 years. Beyond the pleasure of (a small) success, it is also and above all the pleasure of the intellectual groundwork progression that this gave me!

MSX cartridge, it's progressing...

So this time I'm not really making progress in terms of building this MSX cartridge, but I'm tackling all the programming aspects of the future equipped cartridge, which therefore includes an Efinix Trion FPGA.

For now, I've implemented a fairly standard FPGA connector on the MSX cartridge. The problem is that I haven't really experimented with programming Efinix FPGAs using an external JTAG probe. I've simply planned what seems to be the minimum in terms of hardware and am doing all my tests using the JTAG probe on the Efinix development board.

So I got this type of JTAG programming board based on an FTDI 2232H component :

That's about 30 dollars!

Setting up this type of interface involves three steps, after which it will be configured as a JTAG probe by the Efinix programming software:

1.     Configure the hardware resources of the interface.
2.     Install the necessary Windows driver so that the 'new' interface is recognized.
3.     Establish connections with the FPGA's JTAG connector.

For step #1, it is necessary to modify the operating mode of the two ports (A & B) of the FTDI 2232 circuit. To do this, you need to download the FTprog software from the FTDI website, scan for FTDI-type USB interfaces, then configure the two ports as follows:

You just need to configure both ports A & B in 245 FIFO mode. The driver type does not need to be changed. You can also modify the string descriptor to have something more explicit displayed when the interface is detected in the Efinix software. In fact, and after several issues while figuring this out, I copied exactly the same information as that written in the JTAG interface of the development board. The key takeaway, at a minimum, is to configure ports A & B in 245 FIFO mode. 

And that's it. Never modify the VID and PID because after that it may become very complicated to make the FTDI component reachable again by 'standard' software. I had to find a utility on the Internet to perform a 'brute force' erase of the configuration EEPROM, which made it possible to find the interface again using the FTprog software.

For step #2, it is now necessary to modify the drivers for the two interfaces corresponding to ports A & B of the FTDI component. By default, both interfaces are configured with an FTDI driver. To change this configuration, you need to download and install the well-known Zadig utility. You can find documentation on the Internet about its use, which is very simple. At this point, you just need to replace the original drivers of both interfaces with the WinUSB driver. Do this for both interfaces. Because yes, it seems that the Efinix software prefers the JTAG interface to be set up on port B, but doesn't dislike the situation if port A is not also configured like port B. I have no explanation for this, but judging by the messages provided by the Efinix programming interface, I received 'blue' warning messages indicating that a JTAG interface was present on port A but that 'usually' or 'normally' (I'm not really sure), it's better to have it on port B of the 2232 chip. So be it!

I have already done the job, which is why the driver shown is already the WinUSB driver on the left side of the window. Initially, at this location, you will see the FTDI driver.

After these modifications, you will get the two interfaces shown like this in the devices:

'Trion T20 Development Board' is the information I entered into the new FT2232H chip using the FTprog software.

For step #3, All that remains is to connect this new JTAG interface to the Efinix development board. Nothing complicated, except that you still need to be careful about certain points that are not really detailed in the documentation.

The first point concerns the JTAG interface integrated into the development board. I haven't mentioned it until now, but I am using the T20 BGA 256 board. This board has a JTAG connector that is connected on one hand to the FTDI 2232H chip integrated into the board, and on the other hand directly to the FPGA's JTAG port. Since there cannot be two masters on board, you absolutely must disable the internal JTAG interface of the development board. The JTAG connector has a pin labeled 'FRST' which, as its name seems to indicate, stands for FtdiRST. Simply connect this pin to ground by connecting it to the ground pin located right next to it. 

Then, simply connect the classic JTAG signals, namely TMS, TCLK, TDI, and TDO, between the external JTAG probe and the JTAG connector of the development board, not forgetting to connect ground. And... it's almost done.

Yes, almost done, but not quite. In its current state, you will be able to use this external probe, which will be properly recognized by the Efinix programming software. You may even be able to read the FPGA's identification number on your board, but you will not be able to program it.

Because 'the funny thing' is that the Efinix software must temporarily put the FPGA into RESET before starting its programming. I searched through quite a few docs to find out why the Efinix programmer could successfully read the FPGA's ID but was unable to program it, and it took me a little while to find the answer.

Well, in fact, another pin of the FTDI chip is used to reset the FPGA: it's pin ADBUS4 of the 2232H. 

Follow the arrows.

The two points indicated by arrows need to be connected. The goal is to bring the ADBUS4 pin to 'the' available pin on the external JTAG connector. For your information, the JTAG interface I received is version V3.6, and you can find its schematic at this location: GitHub

I simply used a small piece of wire to connect these two points on the solder side. Once the board is put back in its case, this wire is unlikely to move or potentially break a solder joint.

 Simple, isn't it?

Following all these steps, simply summarized here but which actually took me quite some time, I was able to program the FPGA of the development board in JTAG mode without any issues. That was a good start. But you are certainly aware that while this allows the FPGA to be configured, it is a dynamic configuration stored in the FPGA's internal RAM. As soon as the FPGA is reset, it cannot find a configuration file because the external EEPROM has not been programmed. And you are also certainly aware that it is possible to program an external EEPROM connected to the FPGA via the JTAG port of the same FPGA. This is a specific programming mode that the Efinix software allows you to use.

The advantage of this system is that to be able to develop, meaning to quickly modify the FPGA's RAM, the JTAG interface does that, and once development is complete, it is also possible to program the final firmware into the EEPROM using the same JTAG interface. There is no need to provide an additional SPI interface to access the external EEPROM. 

So I programmed the Drumulator firmware, which I am still developing, into the EEPROM of this board using the JTAG port, and here is the result :
 

Better than a long speech: it works!

After these adventures, I now have all the elements to continue working on my MSX cartridge. However, I need to add the RESET pin to the JTAG connector because that is not the case for now.

If you have read this article, I hope you found it useful. Not that everything described here is complicated — and it isn't — but when you don't know about it, it's much less straightforward to grasp.