Drumulator and Efinix FPGA.

A month after my last publication on the subject, a little progress...

And yes, I spent a lot of time on the EMU1 motherboard which, if it still doesn't work, gave me a lot of its secrets which will hopefully allow me to make it work again!

I am therefore resuming the implementation of the Drumulator in an FPGA. This time I test the small simulation board of the machine control panel.

In fact, I have a few issues that I didn't expect with this FPGA. Certainly, its cost is affordable compared to other offers on the market. But I discovered a pretty significant limitation of the implementation of these Efinix FPGAs.

In principle, it is of course possible to do the same thing as any other FPGA with the Efinix Trion range, except that...

It's not that simple. The internal resources are not as flexible as what you can find on other components, which means you have to rethink your way of doing things somewhat..

Basically, asynchronism is not the strong point of these circuits. Well, you will tell me that when we do FPGA, it is not to do asynchronous. Yes... or no. Actually it depends...

Well with the Trion range, the question does not arise : it's 'nyet, tovarishch' !

Once it is well integrated, you just have to review the design. And to validate my 'new' approach, I simply coded a basic Z80 system, accompanied by a very small program allowing me to test the display of the front panel of the Drumulator :

Which allows me to validate not only my way of doing things synchronously now, but also the functioning of the display system.

I can now get back to studying the CTC equipping the Drumulator and conductor of the entire machine.

The next goal is to obtain the same display directly from the Drumulator environment, that is to say with not only the CTC programmed in VHDL, but also the entire generation and reading of the interrupt vector, as well as than his acquittal. I admit that this whole vectorized IRQ system of the Z80 is still a 'happy mess' ;-)

I have (unfortunately) been working again for a few months in national education. Which leaves me less time to do electronics. I still hope to be able to make significant progress on the subject in the coming weeks...

EMU 1 : Finally a first hope?

Same title as the previous post? Indeed, the chain of discoveries continues...

In fact, after discovering a faulty memory component and replacing it, I found that the EMU1 boot process still would not initialize.

What to do then? To get to this point, I set up a serial communication with a PC using port B of the SIO component. It is port A of this component that manages access to the floppy drive. So I considered that this SIO was fully functional since I had no problems with this serial connection.

Not really knowing what to do anymore, I then decided to test port A of this SIO by programming it exactly the same way as port B. The Emu1 schematic means that in fact, it is the same clock speed that drives the writing to the floppy drive. Happy coincidence. So, I have absolutely nothing to change in my code, except just the access addresses to port A.

And then there: surprise!

I had a lot of trouble getting characters to display on the screen. As for getting strings to display: impossible. So I ran a whole series of tests to try to figure out what might be going on.

The conclusions are as follows: When powering up, more than 90% of the time I do not have the characters displayed. And above all, reading the status register seems to pose real problems.

Even though the character was emitted, the empty transmit register bit is never set. So my test program crashes on this, and I can't emit a complete character string.

So: I think the original SIO on the EMU1 board has a malfunctioning port A. Which fits perfectly with the current state of the board that won't boot at all. I have another SIO that I've never gotten anything to output. I assumed it was fine. I've done a lot of testing with it, which has led me to a bunch of wrong assumptions.

What now? I can't really move forward on this. I absolutely need to find some working 8442 type SIO circuits to check if the current state of my assumptions is correct or not!

The hunt for 8442 is on...

Come on, I ordered 5 SIO2 8442 circuits. I just have to wait for them to resume testing...

EMU 1 : Finally a first hope?

Since my last post, I have finalized the EMU1 motherboard DRAM test program.

The problem that arose when testing a 64KB bank and then the other 64KB bank was the management of the variables of my small application. Indeed, by switching banks, we completely lose the contents of variables, which can only crash the program.

How to do it then? One possible answer might be: no global variables to avoid fixed references, use the stack, and switch banks only from the main loop, never in a subroutine.

This way, you can use as many variables as you want, and the stack pointer is necessarily at its origin when you are at the highest point in the program: easy!

And that's how I was able to complete my program, and then test it with two DRAM circuits removed from the board.

I set up a small menu to launch the test, then to choose which bank to test. And on the terminal output, we can clearly see the two missing circuits, which therefore generate two errors.

If we look at how the memory circuits are placed on the motherboard, we have this:

Which corresponds to the following logical organization:

I could have clearly indicated the address where the errors are found but converting from numbers to hex strings takes a lot of resources, in the little program space available, less than 1KB, it is impossible to implement. So, I simply indicate in which 16K segment the defective memory component is located.

If I take the example above, where the indication was RAS2/RAS6, knowing that I had previously selected bank no. 1, I know exactly where the faulty circuit is located.

And that in addition the crash occurs with the processing of 0xAA, I only have to target the four circuits corresponding to the '1' of 0xAA, that is: 0b10101010, or bits 1, 3, 5, 7.

Obviously, if there are more bits in error, this will involve testing all 8 circuits that make up the 16KB segment. But hey, it's already much more practical than just knowing that there is a problem on one of the banks...

So what, you ask? Apparently, I am now able to determine that there is no RAM problem, in fact. Because when I put the two circuits back in place, obviously, I no longer had any errors. Yes, except that...

That's when I decided to configure my program to test absolutely all memory addresses. To do this, I placed the memory stack at the minimum possible RAM space according to the number of bytes needed for my program. In fact, by successive tests, I placed the stack one byte above the value where the program crashes, at 0x040C. As a reminder, the first 0x0400 addresses are those of the ROM. The RAM therefore starts at 0x0400, and I placed the stack 12 bytes higher. Then, I configured the RAM scan to start just above the stack, at 0x040D.

And what do you think happened?

I have several bits in error on the RAS4 segment, since if you run the entire test, you see that I had first performed the test on bank 0 which had not generated any errors, then I selected bank n°1 to relaunch the test which generated these errors.

In fact, and as I was in the process of writing my program, I was able to test the RAM by starting the scan at different addresses. What I determined is that at 0x040E, I have the problem with 0x55 and that at 0x040F I have the problem with 0xAA. I am not able to know if it is the same component that is causing the problem. I am obliged to test the 8 circuits.

On the other hand, I don't know where the EMU program is stored, in bank 0 or 1. I also don't know how the two banks are used by EMU. At 27KHz, and given for 2 seconds of sampling, it seems obvious that only 64Ko are used for sound reproduction, and not 128K. In any case, if the EMU1 program is stored from the base of RAM in bank 1, then there is a guaranteed crash.

At least for the first time, I have a small lead to follow for the resolution of the machine startup problem. In addition, I am pretty sure that the CTC, the SIO and the PIO fulfill their function since to be able to communicate by serial link, I was forced to program these three circuits. And their operation corresponds to what was expected. I should also add that I also tested all the RAM circuits using a small DRAM tester of this type :

As for the EPROM programmer used in component test mode that did not detect a faulty 74ls00, would I be a victim of the same tool reliability problem? Hmm...

So....

EMU 1 : Finally a 'real' first program!

Of course, this may raise a smile, but it wasn't easy to get there!

This allowed me to verify that the serial interface was working in both directions, as well as that there were no errors on the first 64KB bank of RAM.

I still have to check the second bank. I don't know how to do it at the moment, since it will be necessary to do bank switching, otherwise my program will crash miserably.

EMU 1 : Second attempt to write a program for the EMU1 motherboard

I think I finally found the problem of adapting the EPROM emulator. It must be said that it is not particularly easy to adapt an emulator that can only emulate at least a 2764 EPROM on a system designed for a 2708 EPROM!

This is not a problem with my EPROM adapter addressing, but with how the EPROM emulator works internally. For a 2764, it is absolutely necessary to send it 8KB of data otherwise, part of the code is simply not available at the output of the EPROM Emulator.

The usual little loop of sending strings through the serial port. This time the message is big enough to crash the system, but it seems to work.

It took several steps to be able to start working correctly with this EMU1 motherboard!

Well, tomorrow I'm programming the character reception in order to try to lay the foundations of a micro debugging system. I hope that what I've modified about the EPROM emulator will confirm the validity of my approach of today...